FPL 2019 - Field-Programmable Logic and Applications
Monday, September 9th
7:30 Registration opens (closing at 18:00)
8:45 Welcome Message
9:00 Keynote Presentation - Auditorium - Chairperson: Wayne Luk
Mateo Valero, UPC and BSC, "The Barcelona Supercomputing Center"
10:00 Coffee break
10:30 Session M1 - FPGA ARCHITECTURES & TECHNOLOGY - Auditorium - Chairperson: Dionisios Pnevmatikatos
- (10:30, long pres.) "Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage"
Ibrahim Ahmed, Linda Shen and Vaughn Betz
Paper candidate to the Stamatis Vassiliadis Best Paper Award
- (10:55, long pres.) "Bent Routing Pattern for FPGA"
Xibo Sun, Hao Zhou and Lingli Wang
- (11:20, long pres.) "Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency"
Mark Wijtvliet, Jos Huisken, Luc Waeijen and Henk Corporaal
- (11:45, long pres.) "Timing-aware routing in the RapidWright framework"
Leo Liu and Nachiket Kapre
- (12:10, short pres.) "Finding a Needle in the Haystack of Hardened Interconnect Patterns"
Stefan Nikolic, Grace Zgheib and Paolo Ienne
- (12:15, short pres.) "Analysis of Performance Variation in 16nm FinFet FPGA Devices"
Konstantinos Maragos, Endri Taka, George Lentaris, Ioannis Stratakos and Dimitrios Soudris
- (12:20, short pres.) "Measuring Long Wire Leakage with Ring Oscillators in Cloud FPGAs"
Ilias Giechaskiel, Kasper Rasmussen and Jakub Szefer
12:25 Lunch
13:30 Keynote Presentation - Auditorium - Chairperson: Ioannis Sourdis
Walid Najjar, University of California at Riverside, "Why I Love Latency"
14:30 Session A1 - APPLICATION ACCELERATION - Auditorium - Chairperson: Diana Goehringer
- (14:30, long pres.) "Runtime Programmable Pipelines for Model Checkers on FPGAs"
Mrunal Patel, Shenghsun Cho, Michael Ferdman and Peter Milder
Paper candidate to the Michal Servit Best Paper Award
- (14:55, long pres.) "FPGA-based Simulated Bifurcation Machine"
Kosuke Tatsumura, Alexander Dixon and Hayato Goto
- (15:20, long pres.) "On-The-Fly Parallel Data Shuffling for Graph Processing on OpenCL based FPGA"
Xinyu Chen, Ronak Bajaj, Yao Chen, Jiong He, Bingsheng He, Weng-Fai Wong and Deming Chen
- (15:45, short pres.) "Dataflow acceleration of Smith-Waterman with Traceback for high throughput Next Generation Sequencing"
Konstantina Koliogeorgi, Nils Voss, Sotiria Fytraki, Sotirios Xydis, Georgi Gaydadjiev and Dimitrios Soudris
- (15:50, short pres.) "Accelerating Position-Aware Top-k ListNet for Ranking under Custom Precision Regimes"
Qiang Li, Erwei Wang, Shane Fleming, David Thomas and Peter Cheung
- (15:55, short pres.) "Accelerating Physics Engine Components with Embedded FPGAs"
Petros Toupas, Andreas Brokalakis and Ioannis Papaefstathiou
- (16:00, short pres.) "An FPGA-based Architecture to Simulate Cellular Automata with Large Neighborhoods in Real Time"
Nikolaos Kyparissas and Apostolos Dollas
- (16:05, short pres) "Accelerating the merge phase of sort-merge join"
Philippos Papaphilippou, Holger Pirk and Wayne Luk
16:10 Coffee break
16:40 Session A2 - VISION & ARITHMETIC - Auditorium - Chairperson: Peter Cheung
- (16:40, long pres.) "Evaluating the hardware cost of the posit number system"
Yohann Uguen, Luc Forget and Florent de Dinechin
Paper candidate to the Michal Servit Best Paper Award
- (17:05, long pres.) "Extracting INT8 Multipliers from INT18 Multipliers"
Martin Langhammer, Bogdan Pasca, Gregg Baeckler and Sergey Gribok
- (17:30, long pres.) "Efficient Pattern Recognition Algorithm Including a Fast Retina Keypoint FPGA Implementation"
Lester Kalms, Maximilian Hajduk and Diana Goehringer
- (17:55, short pres.) "Quantifying the Benefits of Dynamic Partial Reconfiguration for Embedded Vision Applications"
Marie Nguyen, Robert Tamburo, Srinivasa Narasimhan and James Hoe
18:00 End of Monday sessions
18:00 Reception
20:00 End of Monday
Tuesday, September 10th
8:00 Registration opens (closing at 18:00)
9:00 Keynote Presentation - Auditorium - Chairperson: Christos-Savvas Bouganis
Oskar Mencer, Maxeler
10:00 Coffee break
10:30 Session M2 - ACCELERATED MACHINE LEARNING - Auditorium - Chairperson: Guy Lemieux
- (10:30, long pres.) "A High-performance CNN Processor Based on FPGA for MobileNets"
Di Wu, Yu Zhang, Xijie Jia, Lu Tian, Tianping Li, Lingzhi Sui, Dongliang Xie and Yi Shan
- (10:55, long pres.) "A Flexible Design Automation Tool for Accelerating Quantized Spectral CNNs"
Rachit Rajat, Hanqing Zeng and Viktor Prasanna
Paper candidate to the Michal Servit Best Paper Award
- (11:20, long pres.) "A Data-Center FPGA Acceleration Platform for Convolutional Neural Networks"
Xiaoyu Yu, Yuwei Wang, Jie Miao, Ephrem Wu, Heng Zhang, Yu Meng, Bo Zhang, Biao Min, Dewei Chen and Jianlin Gao
Paper candidate to the Stamatis Vassiliadis Best Paper Award
- (11:45, long pres.) "Accelerating Bayesian Inference for Structured Graphs Using Parallel Gibbs Sampling"
Glenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks and Gu-Yeon Wei
- (12:10, short pres.) "Automatic Compiler Based FPGA Accelerator for CNN Training"
Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvithadhi, Aravind Dasu, Yu Cao and Jae-Sun Seo
- (12:15, short pres.) "InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing"
Shengwen Liang, Ying Wang, Cheng Liu, Huawei Li and Xiaowei Li
- (12:20, short pres.) "FPGA-based Training Accelerator Utilizing Sparseness of Convolutional Neural Network"
Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji and Shimpei Sato
- (12:25, short pres.) "Towards an Efficient Accelerator for DNN-based Remote Sensing Image Segmentation on FPGAs"
Shuanglong Liu and Wayne Luk
12:30 Lunch
13:30 Session A3 - SECURITY - Auditorium - Chairperson: Peter Athanas
- (13:30, long pres.) "Characterizing Power Distribution Attacks in Multi-User FPGA Environments"
George Provelengios, Daniel Holcomb and Russell Tessier
WINNER of the Stamatis Vassiliadis Best Paper Award... Congratulations to the Authors!!!
- (13:55, long pres.) "Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey"
Seyedeh Sharareh Mirzargar and Mirjana Stojilovic
- (14:20, long pres.) "Open-Source FPGA Implementation of Post-Quantum Cryptographic Hardware Primitives"
Rashmi Agrawal, Lake Bu, Alan Ehret and Michel Kinsy
- (14:45, long pres.) "Highly-Portable True Random Number Generator based on Coherent Sampling"
Adriaan Peetermans, Vladimir Rozic and Ingrid Verbauwhede
Paper candidate to the Stamatis Vassiliadis Best Paper Award
- (15:10, short pres.) "Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies"
Farnoud Farahmand, Duc Tri Nguyen, Viet B. Dang, Ahmed Ferozpuri and Kris Gaj
- (15:15, short pres.) "Network Intrusion Detection Using Neural Networks on FPGA SoCs"
Lenos Ioannou and Suhaib A. Fahmy
- (15:20, short pres.) "Beyond the Limits: SHA-3 in just 49 Slices"
Victor Arribas
15:25 PhD Forum papers - Auditorium - Chairperson: Peter Athanas
- (15:25, short pres.) "FPGA Accelerated Deep Learning Radio Modulation Classification Using MATLAB System Objects & PYNQ"
Andrew Maclellan, Lewis McLaughlin, Louise Crockett and Robert Stewart
- (15:30, short pres.) "Spiking row-by-row FPGA Multi-kernel and Multi-layer Convolution Processor"
Ricardo Tapiador Morales, Antonio Rios Navarro, Juan Pedro Dominguez Morales, Daniel Gutierrez Galan and Alejandro Linares-Barranco
- (15:35, short pres.) "A distributed model of computation for reconfigurable devices based on a streaming architecture"
Paolo Cretaro
- (15:40, short pres.) "Neural Network Overlay Using FPGA DSP Blocks"
Lenos Ioannou and Suhaib A. Fahmy
15:45 Coffee break
16:15 Social visit - Temple de la Sagrada Família
Bus service will be provided from Campus to Sagrada Família
20:00 Social Dinner -- Can Cortada
Bus service will be provided from Sagrada Família to Can Cortada
22:30 - 23:00 Busses back to Campus
Wednesday, September 11th
8:00 Registration opens (closing at 18:00)
9:00 Keynote Presentation - Auditorium - Chairperson: Xavier Martorell
Ephrem Wu, Xilinx, "Accelerator Overlays"
10:00 Presentation of FPL2020 - Auditorium
10:15 Coffee break
10:30 Session M3 - MEMORY, NETWORK AND STREAMS - Auditorium - Chairperson: Andreas Koch
- (10:30, long pres.) "DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses"
Mikhail Asiatici and Paolo Ienne
- (10:55, long pres.) "NARMADA: Near-memory horizontal diffusion accelerator for scalable stencil computation"
Gagandeep Singh, Dionysios Diamantopoulos, Christoph Hagleitner, Sander Stuijk and Henk Corporaal
- (11:20, long pres.) "Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow"
Johan Peltenburg, Jeroen van Straten, Lars Wijtemans, Lars T.J. van Leeuwen, Zaid Al-Ars and H. Peter Hofstee
- (11:45, long pres.) "Data stream statistics over sliding windows: How to summarize 150 Million updates per second on a single node"
Grigorios Chrysos, Odysseas Papapetrou, Dionisios Pnevmatikatos, Apostolos Dollas and Minos Garofalakis
- (12:10, short pres.) "Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack"
Mario Ruiz, David Sidler, Gustavo Sutter, Gustavo Alonso and Sergio López-Buedo
- (12:15, short pres.) "System architecture for network-attached FPGAs in the cloud using partial reconfiguration"
Burkhard Ringlein, Francois Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner and Dietmar Fey
- (12:20, short pres.) "Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device"
Seung Won Min, Sitao Huang, Mohamed El-Hadedy, Jinjun Xiong, Deming Chen and Wen-Mei Hwu
- (12:25, short pres.) "High-performance Decoding of Variable-length Memory Data Packets for FPGA Stream Processing"
Roberto Sierra, Filippo Mangani, Carlos Carreras and Gabriel Caffarena
- (12:30, short pres.) "A Dynamic Memory Allocation Library for High-Level Synthesis"
Nicholas Giamblanco and Jason Anderson
- (12:35, short pres.) "A Low-Latency Multi-Version Key-Value Store Using B-tree on an FPGA-CPU Platform"
Yuchen Ren, Jinyu Xie, Yunhui Qiu, Hankun Lv, Wenbo Yin, Lingli Wang, Bowei Yu, Hua Chen, Xianjun He, Zhijian Liao and Xiaozhong Shi
12:40 Lunch
13:40 Keynote presentation - Auditorium - Chairperson: Carlos Alvarez
Suleyman Demirsoy, Intel, "Advancing Ubiquitous FPGA Use"
14:40 Session A4 - ARCHITECTURES & TECHNOLOGY for MACHINE LEARNING - Auditorium - Chairperson: Apostolos Dollas
- (14:40, long pres.) "Specializing FGPU for Persistent Deep Learning"
Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu and Derek Chiou
Paper candidate to the Stamatis Vassiliadis Best Paper Award
- (15:05, long pres.) "A Deep Learning Framework to Predict Routability for FPGA Circuit Placement"
Abeer Alhyari, Ahmed Shamli, Ziad Abuowaimer, Shawki Areibi and Gary Grewal
WINNER of the Michal Servit Best Paper Award... Congratulations to the Authors!!!
- (15:30, long pres.) "Scaling the Cascades: Interconnect-aware mapping strategies for FPGA implementation of Machine Learning problems"
Ananda Samajdar, Tushar Garg, Tushar Krishna and Nachiket Kapre
- (15:55, short pres.) "Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA"
Mário Véstias, Rui Policarpo Duarte, Jose Sousa and Horacio Neto
- (16:00, short pres.) "Reducing Dynamic Power in Streaming CNN Hardware Accelerators by Exploiting Computational Redundancies"
Duvindu Piyasena, Rukshan Wickramasinghe, Debdeep Paul, Siew Kei Lam and Meiqing Wu
- (16:05, short pres.) "TensorFlow to Cloud FPGAs: Tradeoffs for Accelerating Deep Neural Networks"
Stefan Hadjis and Kunle Olukotun
16:10 Coffee break
16:40 Session A5 - TOOLS & METHODS - Auditorium - Chairperson: Luciano Lavagno
- (16:40, long pres.) "OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs"
Xifan Tang, Edouard Giacomin, Aurelien Alacchi, Baudouin Chauviere and Pierre-Emmanuel Gaillardon
- (17:05, long pres.) "Tinsel: a manythread overlay for FPGA clusters"
Matthew Naylor, Simon Moore and David Thomas
- (17:30, long pres.) "Preallocating Resources for Distributed-Memory Based FPGA Debug"
Robert Hale and Brad Hutchings
- (17:35, short pres.) "Low-level Loop Analysis and Pipelining of Applications mapped to Xilinx FPGAs"
Hossein Omidian and Guy Lemieux
- (17:40, short pres.) "Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design"
Hosein Mohammadi Makrani, Farnoud Farahmand, Hossein Sayadi, Sara Bondi, Sai Manoj Pudukotai Dinakarra, Setareh Rafatirad and Houman Homayoun
- (17:45, short pres.) "FPGA Accelerated FPGA Placement"
Shounak Dhar, Love Singhal, Mahesh Iyer and David Pan
17:50 Best Paper Awards Ceremony - Auditorium
18:15 Demo Night & light dinner - Auditorium Hall and Garden
- "Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA"
Takuya Kojima, Naoki Ando, Matsushita Yusuke and Hideharu Amano
- "An FPGA implementation of Real-time Object Detection with a Thermal Camera"
Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi and Hiroki Nakahara
- "Storing Parquet Tile by Tile: Application-aware Storage with Deduplication"
Lucas Kuhring and Zsolt Istvan
- "Demonstration of Flow-in-Cloud: a multi-FPGA system"
Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M M Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma and Hideharu Amano
- "Demonstration of a Multimode SoC FPGA-based Acoustic Camera"
Bruno da Silva, Laurent Segers, An Braeken and Abdellah Touhafi
- "Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs"
Younmin Bae, Ramyad Hadidi, Bahar Asgari, Jiashen Cao and Hyesoon Kim
- "ZytleBot: FPGA integrated development platform for ROS based autonomous mobile robot"
Yasuhiro Nitta, So Tamura and Hideki Takase
- "Realtime Object Detection for Many Pedestrian Toward Surveillance Camera"
Akira Jinguji, Youki Sada and Hiroki Nakahara
- "The CEDARtools Platform -- Massive External Memory with High Bandwidth and Low Latency under Fine-Granular Random Access Patterns"
Thomas Preußer and Alexander Weiss
- "A Self-Calibrating True Random Number Generator"
Adriaan Peetermans, Milos Grujic, Vladimir Rozic and Ingrid Verbauwhede
- "The FOS (FPGA Operating System) Demo"
Anuj Vaishnav, Khoa Pham, Kristiyan Manev and Dirk Koch
Sponsors Demos
- Xilinx Demo: "Demonstration of Classification and Detection based on FPGA Accelerator of MobileNets"
Di Wu, Yu Zhang, Jinzhang Peng, Haotian Guo, Dongliang Xie and Yi Shan
- Maxeler Demo: "MaxIDS: Maxeler Intrusion Detection System on a miniMAX DFE"
Tobias Becker