FPL2019 Keynote Speakers

Prof. Mateo Valero, Barcelona Supercomputing Center and Universitat Politècnica de Catalunya

 

 

 

 

 

 

"The Barcelona Supercomputing Center"

Abstract

The BSC-CNS, Barcelona Supercomputing Center-Centro Nacional de Supercomputación, was established in 2005 and houses the MareNostrum, one of the most powerful supercomputers in the world. We are the pioneer center of supercomputing in Spain. Our specialty is High Performance Computing - also known as HPC - and our mission is twofold: to offer infrastructure and supercomputing services to Spanish and European scientists, and to generate knowledge and technology to transfer them to society. We are a Severo Ochoa Center of Excellence, which recognizes us as one of the best research centers in Spain, members of the first level of the European research infrastructure PRACE (Partnership for Advanced Computing in Europe), and we manage the Spanish Supercomputing Network (RES). As a research center, we have more than 600 experts, with more than 40% from 48 countries, organized into four major areas of research: Computer Science, Life Sciences, Earth Sciences and Computer Applications in Science and Engineering.

We have a close collaboration relationship with the industry and especially with leading companies in the information technology sector and users of supercomputing. This relationship has been reflected, among other agreements, in the creation of joint research centers with companies such as IBM, INTEL, Microsoft, Nvidia, and Repsol. The center has been very active in the EC Framework Programs and has participated in more than 150 projects funded by Brussels. In this talk I will explain some of the research projects we developed with the aforementioned companies, others within the European context and others of an internal nature to the BSC. I will also explain the three major challenges we are facing today, such as the use of supercomputers for Artificial Intelligence, for Personalized Medicine and finally the development of the European supercomputer.

Bio

Mateo Valero obtained his Telecommunication Engineering Degree from the Technical University of Madrid (UPM) in 1974 and his Ph.D. in Telecommunications from the Universitat Poltècnica de Catalunya (UPC) in 1980. He is a professor in the Computer Architecture Department at UPC, in Barcelona. His research interests focuses on high performance architectures. He has published approximately 700 papers, has served in the organization of more than 300 International Conferences and he has given more than 500 invited talks. He is the director of the Barcelona Supercomputing Centre, the National Centre of Supercomputing in Spain.

 

Prof. Walid Najjar, University of California, Riverside

"Why I came to love memory latency"

Abstract

Memory latency has been a constant challenge in computer architecture designs. Elaborate cache hierarchies are designed to mitigate the memory latency. These cache architectures consume a disproportionate fraction of the chip area and the power and thermal budget of the chip. Furthermore, cache architectures assume the existence of some form of spatial and/or temporal locality. However, modern applications operating on very large multi-dimensional data sets exhibit very little locality.

Latency masking is an alternative to latency mitigation that relies on trading latency for bandwidth by masking the cost of memory accesses. It is not a new approach and has been implemented in a number of general purpose computer architectures, such as barrel processors.

In this talk I will describe the poof of concept implementation of the filament execution model that relies on latency masking to accelerate large scale data analytics applications.

Bio

Walid A. Najjar is a Professor in the Department of Computer Science and Engineering at the University of California Riverside. His areas of research include computer architectures and compilers for parallel and high-performance computing, embedded systems, FPGA-based code acceleration and reconfigurable computing.

Walid received a B.E. in Electrical Engineering from the American University of Beirut in 1979, and the M.S. and Ph.D. in Computer Engineering from the University of Southern California in 1985 and 1988 respectively. From 1989 to 2000 he was on the faculty of the Department of Computer Science at Colorado State University, before that he was with the USC-Information Sciences Institute. He was elected Fellow of the IEEE and the AAAS.”

Dr. Oskar Mencer, CEO/CTO, Maxeler

 

"Commercializing Software for FPGAs"

Abstract

FPGAs (and FPL) have been around for many decades now, driving a large community in research. In this past year, we witnessed a change in focus from FPGA vendors on datacenter applications, and the encouragement of an ISV eco-system. What are the current opportunities and obstacles of taking cutting edge research and transforming it into commercial success? What are the historical lessons learned and options for the next decade? Drawing on 16 years of experience in commercializing software for FPGAs in the Datacenter, both private and public cloud, this talk explores possible
business models of major FPGAs vendors and how the FPL community can prepare the output of their research efforts to fit into the newly created business processes.

Bio

Oskar Mencer is the Founder and CEO of Maxeler, affiliated with the Computing Department at Imperial College London and Member of Academia Europaea. Oskar is driving the deployment of operational excellence for data processing via a new science of Multiscale Dataflow Computing and Space-Time-Value discretization. Prior to Maxeler, Oskar was in Computer Sciences (1127) at Bell Labs in Murray Hill, Stanford University and Hitachi Central Research Laboratory in Tokyo. Oskar received two Best Paper Awards, an Imperial College Research Excellence Award in 2007, and a Special Award from Com.sult in 2012 for "revolutionising the world of computers".

Ephrem Wu, Senior Director in Applied Architecture, Xilinx

"Accelerator Overlays - Spec What You Want, Build What You Need"

Abstract

FPGAs and ACAPs enable hardware architects to build software-programmable accelerator overlays for different applications on the same platform. Hardware designers implement virtual accelerators on these reconfigurable devices, abstracting hardware synthesis and physical design away from compiler developers and accelerator programmers. Using examples from communications and machine learning, we will discuss how domain-specific accelerators bring the power of parallel hardware to software programmers.

Bio

Ephrem Wu is a Senior Director in Applied Architecture at Xilinx. Ephrem joined Xilinx in 2010, when he spearheaded the design of the first 2.5D FPGA with 28 Gb/s transceivers. Since then, Ephrem led the definition of the UltraRAM and the Versal DSP. His current focus is machine-learning accelerators for machine vision and machine translation. From 2000-2010, Ephrem led backplane switch and security processor development at Velio Communications and LSI. Prior to Velio, he developed ASICs and DSP software at SGI, HP, Panasonic, and AT&T. Ephrem holds 32 U.S. patents. He earned a bachelor's degree from Princeton University and a master's degree from the University of California, Berkeley, both in EE.

 

Dr. Suleyman Demirsoy, Acceleration Architect, Intel

"Advancing Ubiquitous FPGA Use in HPC and Algorithmic Acceleration"

Abstract

FPGAs are becoming mainstream. Large data center deployments, cloud availability and higher level programming models are all working to expand FPGA accessibility to an increasing number of developers. With the new user base comes demand for readily-accessible, FPGA-optimized libraries; usable without knowledge of traditional low-level FPGA development languages and tools. We see new challenges for this broader user base; including composing large performant designs from library functions, ease of use and differentiation against other types of acceleration.

In this talk, Dr. Demirsoy will touch on what it takes to enable FPGA at a large scale in algorithmic acceleration,  how high level tools and new data access models are addressing the challenges faced by the developer community for FPGA-based acceleration and share his viewpoint on strategies for differentiation at a platform and chip level as well as on building performant libraries.

Bio

Dr. Suleyman Demirsoy is an Acceleration Architect for Intel FPGAs covering Enterprise and HPC acceleration markets in EMEA.  He has a PhD in digital signal processing and 15 years' experience creating real-world FPGA system solutions for customers across military, industrial, wireless, financial and high-performance computing. Suleyman is a member of the Intel's technical leadership program. Outside Intel, he serves in the advisory boards of several startups and as a board member for London Innovation Society, a non-profit organization promoting entrepreneurship and innovation in the technology community.