Chisel Tutorial at FPL2019

Hardware Design in the 21st Century with the Object Oriented and Functional Language Chisel

(With FPL 2019)


Organizer: Martin Schoeberl (DTU)


To develop future more complex digital circuits in less time we need a better hardware description language than VHDL or Verilog. Chisel is a hardware construction language intended to speedup the development of digital hardware and hardware generators.

Chisel is a hardware construction language implemented as a domain specific language in Scala. Therefore, the full power of a modern programming language is available to describe hardware and, more important, hardware generators. Chisel has been developed at UC Berkeley and successfully used for several tape outs of RISC-V. Here at the Technical University of Denmark we use Chisel in the T-CREST project and in
teaching advanced computer architecture.

In this tutorial I will give an overview of Chisel to describe circuits at the RTL level, how to use the Chisel tester functionality to test and simulate digital circuits, present how to synthesize circuits for an FPGA, and present advanced functionality of Chisel for the description of circuit generators.

The aim of the course is to get a basic understanding of a modern hardware description language and be able to describe simple circuits in Chisel. This course will give a basis to explore more advanced concepts of circuit generators written in Chisel/Scala. The intended audience is hardware designers with some background in VHDL or Verilog, but Chisel is also a good entry language for software programmers entering into hardware design (e.g., porting software algorithms to FPGAs for speeup).

Besides lecturing we will have lab sessions to describe small circuits, test them in the Chisel simulation, and run them in an FPGA.