Intel Tutorial: Expert Design Techniques for OpenCL with FPGAs (full-day)

This hands-on workshop will cover techniques for generating high performance solutions on the FPGA using the Intel(r) FPGA SDK for OpenCL. We will examine how kernels are converted to custom dataflow circuits and how executions of the OpenCL kernels are mapped onto the FPGAs. We will experiment with various debug and analysis tools available in the SDK to help us optimize our OpenCL kernels with regards to both FPGA resource consumption and performance.

We will examine how loops in kernels can be effectively optimized for deep pipelined-parallel execution. We will discuss how local memory systems can be generated on the FPGA for effective stall-free accesses from kernel. We will practice stream data in and out of the kernels using pipes and channels from the host, external interfaces, and other kernels for effective inline acceleration. We will guide the compiler to make performance and area tradeoffs through use of attributes and pragmas and arbitrary-precision data types.

Finally, we will review several design patterns and how to express them efficiently by using a combination of the techniques presented so far and dissect how these concepts were applied to a showcase design.

Attendees should have basic familiarity with OpenCL.